SV1 Architecture
ìSingle Stream Processorsî (SSPs)
300 MHz clock (3.33 ns clock period)
Four SSPs per module board
- Total module-to-memory bandwidth is about 5 GB/sec
- Each processor can access at most 2.5 GB/sec
Dual-pipe floating-point units
- Can produce two add-multiply results per clock period
- Scalar operations share one of the pipes
Theoretical peak performance: 1.2 GFLOP/sec per SSP
Eight scalar and eight vector registers
Vector length of 64 words