Goals

To gain insight into performance issues arising from the new architectural features of the SV1

• Vector cache
• Multi-stream processors (MSPs)

To begin to study how these performance issues will impact the migration of codes, developed for Y-MP/C90/T90 series machines, to Cray’s new architecture roadmap

To characterize the machine performance on a variety of real-world applications

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• Leadin: There were 3 motivating factors that led us down this path