SV1 Architecture

5.0 GB/s

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• Leadin: Iinternally there are cpus and cpu module boards. Four cpus reside on a given module board.

• -Each module board has an independent connection to memory. The effective module board to memory bandwidth is ~5 gb/s.

• -From cache to main memory, each SSP can access 2.5 gb/s.

• -If all 4 processors have an application running, the combined 4 have to share the 5 gb/s restriction