The Multi-Stream Processor

Four SSPs configured to act like one super-processor

4.8 GFLOP/sec theoretical peak performance

Cache coherency currently a significant performance bottleneck

Shared B and T registers

Configured using one SSP from each of four module boards to achieve optimum access to main memory

Minimizes contention for bandwidth to main memory
Net memory-to-MSP bandwidth: ~10 GB/sec

The SV2 will consist entirely of MSPs

Previous slide Next slide Back to first slide View graphic version

Notes:

Leadin: That touches on the changes to the memory system. The other siginificant change is the introduction of the Multi-Stream processor

-In addition to combining the floating point performance of 4 processors, the cache and registers are effectively increased as well

-Currently cache coherency is handeled in software, which limits some data reuse

-To satisfy the increased memory requirements, the MSP is constructed from SSP processors on seperate module bds