Memory Bank Conflicts
Traditional Cray vector computers fetch vector operands directly from main memory, so the potential for memory bank conflicts is very sensitive to the way algorithms step through memory
The SV1 vector cache now resides between memory and the CPU and it can have a significant mitigating effect on bank conflicts
- Ability to pre-fetch data into the cache
- Data may be resident in the cache, eliminating fetches to memory
- Cache can significantly improve performance when stride is power of two
- Cache only helps; performance is never worse than “cache off” scenario
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Notes:
- In addition to minimizing cache utilization, memory bank conflicts remain a performance issue.
- The vector cache, however, has the additional benefit that it can hide some of the effects of memory bank conflicts.